Methods of forming field effect transistors typically include steps that utilize sidewall spacers on gate electrodes as implant masks to define self-aligned source and drain regions within a semiconductor substrate. However, as the degree of integration of field effect transistors within integrated circuits continues to increase, the spacing between adjacent gate electrodes frequently decreases. As will be understood by those skilled in the art, this decrease in spacing between adjacent gate electrodes may cause the formation of unwanted material residues (e.g, insulating material) in the spacing during deposition and etch-back of sidewall spacers. To address this problem, sacrificial sidewall spacers have been used to reduce the likelihood of formation of material residues by increasing the effective spacing between adjacent electrodes. Unfortunately, many sacrificial sidewall spacers may be formed of materials that do not support sufficient etching selectivity relative to surrounding materials. Accordingly, the use of conventional sacrificial sidewall spacer materials may not provide sufficient prevention of material residues during fabrication.